ADCs, either stand alone or as an embedded module in a processing system, are used in a variety of applications for converting analog signals to their digital equivalent signals. Within an ADC, RDACs (resistor digital-to-analog converters) have been used to convert digital signals to its analog equivalents within ADCs. The converter process typically proceeds by an input signal or derivation thereof being compared with a reference signal generated by an RDAC. Through multiple comparisons the input signal is approximated by a digital value. The RDAC configuration may be one of several configurations. For example, the resistors of an RDAC may be aligned in series or in parallel, may have differing values, and may be replaced with capacitors. The configuration of the resistors or the capacitors in an RDAC are generally optimized in order to reduce the RC (resistor capacitor) delay associated with such a configuration. Several alternative configurations have been used to reduce this RC delay. For example, a sampling capacitor located at the output of the digital-to-analog converter can be reduced, while other components such as the resistors in the RDAC may also be smaller. In addition, a total equivalent resistance of the network may also be reduced. However, these alternative configurations cause several problems. First, the reduction of the sampling capacitance reduces the accuracy of the digital-to-analog conversion. Placement of the resistors in parallel rather than in series requires more power in the system. Accordingly, a need exists to create an RDAC and RDAC configuration that reduces the RC delay without these disadvantages of the prior art. In particular, a need exists for a technique for reducing the RC delay that may utilize a digital solution rather than an analog solution in order to simplify the RDAC process.